Phase-locked loop (PLL) frequency synthesis is a well known technique for generating one of many related signals from a voltage controlled oscillator (VCO). In a single loop PLL, an output signal from the VCO is coupled to a programmable frequency divider. The programmable frequency divider divides by a selected integer number, providing a frequency divided signal to a phase detector. The phase detector compares the frequency divided signal to a reference signal from another fixed frequency oscillator. Any difference in phase between the frequency divided signal and the reference signal is output from the phase detector, coupled through a loop filter, and applied to the VCO. The phase difference signal causes the output signal from the VCO to change in frequency such that the phase error between the frequency divided signal and the reference signal is minimized. Since the programmable divider divides by integers only, the step size of the programmable divider constrains the output frequency. With the single loop PLL, an engineering compromise must be struck between the competing requirements of loop lock time, output frequency step size, noise performance, and spurious signal generation.
In order to overcome the limitations of the single loop PLL, programmable frequency dividers capable of dividing by nonintegers have been developed. Output frequency step sizes which are fractions of the reference signal frequency are obtained while maintaining a high reference frequency and wide loop bandwidth. A discussion of fractional-N synthesis may be found in U.S. Pat. No. 4,816,774. As described therein, two accumulators are employed to simulate the performance of fractional synthesis. The simulation switches between different integer values of divisors without the attendant spurious signals generated by such switching. The two accumulator technique acts to reduce the unwanted spurious signals by cancellation and loop filter rejection.
The reference signal frequency for the fractional-N frequency synthesizer is, therefore, determined by the step size of the VCO output frequency multiplied by the denominator of the programmable divider divisor. Fractional-N synthesis allows the use of a reference frequency which is much higher than the actual channel spacing and allows designs to use wider bandwidths due to the reduction of low frequency spurious outputs. Wider bandwidths allow fast lock times and the possibility of wideband modulation applied to the reference input or the fractional division scheme.
Unfortunately, the system is not perfect and generates some spurious signals output at a frequency equal to the channel spacing. The desired signal output purity is better than the nonfractional system, but by itself may still be insufficient for some high quality systems.
In order to minimize the effects of this spurious output, multiple accumulator fractional-N synthesis systems have been developed. These systems spread out the spurious signals to frequencies at which filtering is inexpensive and simple. By using systems with more than two accumulators this benefit can be dramatically increased.
Some of the present multiple accumulator systems require the accumulators to "ripple" the data. Specifically, on every clock pulse the data must act on the entire digital network. This results in a relatively low upper frequency limit of operation for a multiple accumulator system due to propagation delays in the digital circuitry used to build the system. Finally, some current multiple accumulator systems still maintain a residual noise term which may cause spurious noise signals. These spurious noise signals must be diminished for proper operation of many systems.